RE: [IBIS-Users] rising waveform

There are several different reasons why this can occur.  First is you did
not let the waveform complete its rise (but that does not seem to be the
case here), second the 70 Ohms in the model does not match the load used in
the VT extraction.  Third, the termination voltage used in the extraction
does not match the one in the model.  Forth, the summation of the clamp and
pullup tables does not match the characteristics of the buffer as
simulated., etc.

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

  -----Original Message-----
  From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf
Of lau yy
  Sent: Thursday, July 07, 2005 4:52 PM
  To: ibis-users@eda.org
  Subject: [IBIS-Users] rising waveform


  Dear ALL,

  Can someone show me my mistake? The warning message like below.

  WARNING - Model DQ0: The [Rising Waveform]
        with [R_fixture]=70 Ohms and [V_fixture_max]=3.1V
        has MAX column DC endpoints of  1.74V and  3.10v, but
        an equivalent load applied to the model's I-V tables yields
        different voltages ( 1.71V and  3.10V),
        a difference of  1.94% and  0.01%, respectively.

  Thanks alot.



  rdgs
  yylau
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