Dmitry, I think you said it correctly. Roberto, If the additional delay bothers you, you could remove some of the early, non-changing data points from the IBIS data. On the other hand, it's not necessary and it makes people ask questions, think, and learn..... Aubrey Sparkman Enterprise Engineering Signal Integrity Team Dell, Inc. Aubrey_Sparkman@Dell.com (512) 723-3592 The Greatest Pleasure in Life is Doing what People say can't be done... -----Original Message----- From: Roberto IZZI [mailto:roberto.izzi@st.com] Sent: Friday, January 12, 2007 2:15 AM To: Dimitry Eisenshtat Cc: NG,MEI-YEE; ibis@server.eda-stds.org; ibis-users@server.eda.org; Sparkman, Aubrey Subject: Re: [IBIS] Re: [IBIS-Users] Ibis open drain strange behaviour Hello everybody Thank you very much for your feedback. In my open drain ibis model, I have extracted Rise and fall wave by TX level simulation of buffer (spice) connecting a load resistance value equal to 20K between open drain pad and power. In this case I have considered the real delay between transient of input signal and output. Now if I consider the same input signal (by which I have extracted Rise and Fall tables) for ibis model and the same resistance value (20k), I should have the same behaviour between Ibis and spice buffer. Thanks and best regards. Roberto Izzi Dimitry Eisenshtat wrote: > Hi all, > Mei Yee, if you see the buffer to be modeled as box with some > interface (lets speak for example about one directional buffer which > has only transmitter, so the interface in simplest case will be > data_from_core, enable, pad) - you of course expected from IBIS > representation the same (in ideal case) behavioral as the > transistor-level simulation with spice, in other words, no delay is > expected between both transient responses. But it is the artificial > situation, in real life you are looking from board level and you can > not synchronize your simulation with signal inside the core aren't > you? How you can define for example WHEN the input signal starts the > transition - it dependent on unknown digital stage number the signal > is walking on before the buffer data_from_core input, isn't it ? As i > understand, the delay from enable to pad is meaningless, because > actually you can not define absolute time in board-level scope, only > the transition itself is important. Another question is - why the > delay comes to be, but for example the answer may be the time > windowing of V/T tables (I mean the model maker probably shifts the > transients response table in order to make the time window smaller, > for example). > > I have to say, I'm circuit designer and I has produced a lot of IBIS > models, but has actually no knowledge about using of these models on > board level, so I really like to know if I have a mistake. Aubrey, did > you mean the same things? > > Regards, > Dmitry > > NG,MEI-YEE wrote: > >> Hi everybody, >> I would like to say that I experienced the same phenomenon as >> Roberto, with the IBIS waveform delayed compared to the transistor >> level simulation. Aubrey, what do you mean by IBIS model doesn't >> contain buffer delay? How does that explain IBIS model being delayed >> in the output response? >> >> Appreciate any feedback. Thank you. >> >> Best regards, >> Mei Yee >> >> -----Original Message----- >> From: owner-ibis-users@server.eda.org >> [mailto:owner-ibis-users@server.eda.org] On Behalf Of >> Aubrey_Sparkman@dell.com >> Sent: Friday, January 12, 2007 12:15 AM >> To: roberto.izzi@st.com; ibis@server.eda-stds.org; >> ibis-users@server.eda.org >> Subject: RE: [IBIS-Users] Ibis open drain strange behaviour >> >> Is your only concern the time delay? IBIS and Spice aren't always >> aligned in time since IBIS doesn't contain the buffer delay. >> >> >> Aubrey Sparkman Enterprise Engineering Signal Integrity Team Dell, >> Inc. Aubrey_Sparkman@Dell.com (512) 723-3592 >> >> The Greatest Pleasure in Life is Doing what People say can't be done... >> >> -----Original Message----- >> From: owner-ibis-users@server.eda.org >> [mailto:owner-ibis-users@server.eda.org] On Behalf Of Roberto IZZI >> Sent: Thursday, January 11, 2007 10:08 AM >> To: ibis@server.eda-stds.org; ibis-users@server.eda.org >> Subject: [IBIS-Users] Ibis open drain strange behaviour >> >> Hello everybody >> >> I 'd like to have some information about a strange behaviour of Open >> drain buffer Ibis model. >> I have noticed a mismatch between Transistor level and Ibis model >> voltage output during a transient analysis, considering the same buffer. >> In fact in presence of the same input voltage wave and for a high >> value of load resistance(for example 20Kohm)connected to power, we >> can observe a delay between TL output and Ibis output. In the Ibis >> file, for Open drain, Rise and fall waves tables have been extracted >> considering the same resistance connected to Power (20Kohm). >> What is the cause of this strange behaviour? >> >> Thanks and best regards >> >> Roberto Izzi >> >> >> -- >> This message has been scanned for viruses and dangerous content by >> MailScanner, and is believed to be clean. >> > > > ====================================================================== > ===================== > > The privileged confidential information contained in this email is > intended for use only by the addressees as indicated by the original > sender of this email. If you are not the addressee indicated in this > email or are not responsible for delivery of the email to such a > person, please kindly reply to the sender indicating this fact and > delete all copies of it from your computer and network server > immediately. Your cooperation is highly appreciated. It is advised > that any unauthorized use of confidential information of Winbond is > strictly prohibited; and any information in this email irrelevant to > the official business of Winbond shall be deemed as neither given nor > endorsed by Winbond. > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993Received on Fri Jan 12 08:07:54 2007
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