Subject: [IBIS] IBIS SUmmit minutes 6/13/02
From: Guy deBurgh (gdeburgh@innoveda.com)
Date: Tue Jun 18 2002 - 14:30:08 PDT
DATE: 6/18/02
SUBJECT: June 13, 2002 EIA IBIS Summit Meeting Minutes
VOTING MEMBERS AND 2002 PARTICIPANTS LIST:
Ansoft Corporation (Eric Bracken)
Apple Computer Kim Helliwell
Applied Simulation Technology Fred Balistreri, Norio Matsui*
Cadence Design Lynne Green*, Patrick dos Santos, Lance Wang
Cisco Systems Syed Huq*, Abdulrahmun Rafiq, Zhiping Yang
Cypress Semiconductor (Rajesh Manapat)
IBM Greg Edlund Pravin Patel
Innoveda (Merged with Mentor John Angulo, Guy de Burgh, Steve Gascoigne
Graphics
Intel Corporation Stephen Peters*, Arpad Muranyi*, Will Hobbs,
Pete Block, Ben Silva, Tony Lewis,
Michael Mirmak
LSI Logic [Larry Barnes], Frank Gasparik
Matsushita (Panasonic) Atsuji Ito*
Mentor Graphics Bob Ross*, Ian Dodd, Mike Donnelly,
Matt Hogan, Sherif Hammad, Tom Dagostino,
Eric Rongere, Karine Loudet
Micron Technology Randy Wolff
Mitsubishi Pat Hefferan*
Molex Incorporated Gus Panella
Motorola Rick Kingen
National Semiconductor Milt Schwartz*
NEC Corporation (Akimoto Tetsuya)
North East Systems Associates (Edward Sayre)
Philips Semiconductor (D.C. Sessions)
Quantic EMC (Mike Ventham)
Siemens (& Automotive) AG Helmut Katzier, Katja Koller, Eckhard Lenski*
Signal Integrity Software Barry Katz*, Walter Katz*, Robert Moles,
Daniel Nilsson, Kevin Fisher, Steve Coe,
Wiley Gillmor, Douglas Burns*, Eric Brock,
Sigrity Raj Raghuram
SiQual [Scott McMorrow], Dave Macemon, Rob Hinz
Texas Instruments Thomas Fisher, Jean-Claude Perrin
Time Domain Analysis Systems Steve Corey, Dima Smolyansky
Via Technologies (Weber Chuang)
Zuken (& Incases) Caroline Legendre, Ralf Bruening*
OTHER PARTICIPANTS IN 2002:
3Com (& CommWorks) [Roy Leventhal], James Goshorn
Actel Prabhu Mohan
Agilent Herbert Lage
Airbus Claude Huet
Alstom Transport Luca Giacotto*
Apt Software Atul Agarwal
Astrium Olivier Prieur
Avanti (Hailong Wang)
Bee Technologies Corporation Tsuyoshi Horigome*
Brocade Communications Robert Badal
Compaq Shafier-ur-Rahman
Japan Electronics and Kiyomi Daishido*
Information Technologiy
Industries Association
(JEITA)
EADS CCR Alix de la Villeguerin
EFM Ekkehard Miersch
EIA [Cecilia Fleming], Chris Denham*
EMC Corporation (Brian Arsenault)
Fairchild Semiconductor Adam Tambone
Force Computers Roger Sukiennik
Harman/Becker Automotive Hartmut Exler
Systems
Huawei Technologies (Jiang Xiang Zhong)
Leventhal Design and Roy Leventhal
Communication
National Institute of Applied Sebastian Calvet (& Motorola), Etienne
Sicard,
Science (INSA) Stephane Baffreau
Northrup (Litton) Robert Bremer
Sagam SA Quang Ngo, Matthieu Fontaines
Shindengen Elecric Mfg. Co. [Tsuyoshi Horigome]
Sintecs Hans Klos
STMicroelectronics Fabrice Boissieres
TDK Yoshikazu Fujishiro
Thales Saverio Lerose
Tyco Electronics (Tim Minnick)
UTMC Greg Haynes*
Xilinx Susan Wu, J.L. de Long
Independent Larry Barnes
In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.
Upcoming Meetings: The bridge numbers for future IBIS teleconferences
are as follows:
Date Bridge Number Reservation # Passcode
June 28, 2002 1-888-316-5901 N/A 2358667
(International Dial-in 1-617-801-9781)
All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.
NOTE: "AR" = Action Required.
-------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
The IBIS Summit Meeting was held in New Orleans, Louisiana at the Hilton
Riverside Hotel. This IBIS Summit Meeting is held during the Design
Automation Conference (DAC 2002) at the adjacent Ernest N. Morial Convention
Center. About 19 people representing 14 organizations attended.
The notes below capture some of the content and discussions. The meeting
presentations and other material is uploaded at:
http://www.eda.org/pub/ibis/summits/jun02/
Stephen asked everyone in the room to introduce themselves. The group was
well represented by semiconductor vendors and model providers, EDA tool
vendors, and users of IBIS models. Stephen thanked the presenters and
participants for attending.
Stephen asked if there were any new issues or discussion items to put on
the agenda.
Finally, Stephen thanked the presenters and participants for attending and
started with the presentations.
Also, Matsushita (National/Panasonic) joined the EIA IBIS Open Forum as a
new member.
PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions. These
notes capture some of the content and discussion. More detail are in the
uploaded documents noted above.
IBIS ANNUAL REPORT
Stephen Peters, Intel Corporation
Stephen Peters opened the presentations with a summary of today's meeting,
a look back at the previous year, and a look ahead at the coming years
challenges. Stephen noted that IBIS 3.2 is truly an international
standard, as evidenced by European and Japanese interest, and that
despite the weak economy the IBIS Open forum membership remained constant
at about 30 paid members. The organization remains financially healthy.
Significant events this year include the formation of the IBIS Quality
group, a move to Majordomo for mailing list maintenance, and the shift
from IBIS-X to the Multi-lingual modeling proposal. The biggest
challenges for the coming year include enabling the roadmap into the
future via passing IBIS 4.0, the Interconnect Specification and
the Multi-lingual modeling proposal. The IBIS Open Forum must also
continue to work to improve model quality. Stephen would also like to
continue to track European EMC/EMI developments and determine the need
for XML based parsers. Finally, Stephen offered his thanks to the officers
and other members of the organization for there support and help during
the past year.
IBIS QUALITY CHECKLIST
Barry Katz, Signal Integrity Software (SiSoft)
Barry Katz opened the presentation by recapping the IBIS Quality group's
charter. Barry went on to state that the first goal of the model quality
group is to have the model quality checklist available for review at the
next summit meeting in September. Arpad Muranyi asked if the checklist will
address shortcomings in the IBIS specification itself. Barry answered
that it will not address shortcomings directly, but specification
improvements will comes as a natural part of looking at quality. Barry
estimates that the checklist will cover up to 95% of common model problems.
Barry noted that the quality committee is looking at the establishment of
levels of model quality and has also submitted an IBIS golden parser open
source proposal.
Walter Katz stated that he would like to see a process whereby waveform
checks keywords (waveform rules) could be quickly added to specification.
The specific example of adding keywords that define eye diagram measurement
metrics (for example, output jitter) was mentioned. Arpad Muranyi
suggested one way to add this functionality was to define several
variables, then allow a user to assign values to them. Discussion continued
on a proposal to add a [User] keyword that can be followed by vendor
specific measurement statements. Stephen Peters asked if the goal was to
give a model creator the ability to programmatically define specific
measurements or simply provide a spec value. Walter replied that he expects
the EDA software to remain responsible for doing the measurements.
LVDS IBIS MODELS @ 1.25GHZ
Douglas Burns, Steven Coe, and Kevin Fisher, Signal Integrity Software
(SiSoft)
Douglas Burns began this presentation by asking if IBIS models are valid at
Ghz frequencies. He believes the answer is both yes and no: it depends on
the model and understanding where models are valid and where they are not.
Barry noted that the IBIS prototype model is fundamentally a single ended
model. Barry went on to describe a three step process for gathering data
from a differential output buffer suitable for use by two single ended
models. First, one has to connect the buffer to a load and determine the
common mode output voltage (Vcm). Step two is to sweep Vout on one output
pad while sweeping the other with an opposite polarity voltage, all the
while
keeping Vcm constant throughout. Such a sweep will keep constant current
flowing thru the device's output. Douglas emphasized that by gathering data
in this fashion one is assuming that the buffer has symmetrical drive
strengths high and low. The final step is to convert the resulting I-V data
to IBIS format. Douglas went on to show very good correlation between the
resulting IBIS model and the transistor level model. However, he did note a
potential issue with this modeling method -- some simulators may not like
the fact that I-V table does not contain a 0,0 point, and may automatically
try and 'correct' the table. Douglas also showed that the created model is
only valid (accurate) at a particular VDDQ conditions. This is because the
LVDS model assumes constant Vcm and device symmetry.
Arpad Muranyi mentioned a technique he is exploring that uses some of the
[Series] keyword elements to create differential buffers. The idea is to
build a model that accurately models both the common mode and differential
mode impedance of the buffer. However, Arpad commented that there he still
has more work to do in this area. The bottom line is that it is possible to
model an LVDS buffer at Ghz frequencies using IBIS, but the model is
accurate only for specific conditions.
ELECTION OF OFFICERS FOR 2002-2003:
Stephen Peters opened the meeting for nominations for each of the six
officer
positions starting with Chair, Vice-Chair, Secretary, Webmaster, Postmaster,
and Model Librarian.
Each officer was nominated and elected by acclimation unopposed.
The following officers were elected for 2002-2003:
Stephen Peters, Chair
Lynne Green, Vice Chair
Guy de Burgh, Secretary
Syed Huq, Webmaster
John Angulo, Postmaster
Roy Leventhal, Model Librarian
IBIS-MODELS TODAY, THEIR PARAMETERS AND THEIR ACCURACY
Eckhard Lenski, Siemens AG
Mr. Lenski began his presentation by suggesting a number of new keywords
that would support modeling of new component features. Eckhard described a
component with a control pin that enables the user to configures the
device's inputs as either differential ECL or single ended TTL. To enable
modeling of such a component Eckhard proposed adding a [Diff Model
Selector] keyword to the specification. Eckhard also noted that IBIS
cannot specify the Vinh/Vinl levels of a receiver intended for use in
multi-level signaling logic. Eckhard suggested some kind of if-then-else
construct be added to the specification for use in specifying valid input
levels. He then went on to describe the case of an I/O buffer where the
input buffer path contains a series resistor that is not present in the
output path. Because there is only have one set of clamp curves for a
"pin", there is no way to describe the extra clamp current when buffer is
receiving. Finally, Eckhard asked if it was OK to include overshoot and
undershoot parameters when describing an output buffers. Bob Ross replied
that there was nothing in the specification that prevented this, and it
should not be prohibited by the parser.
On the subject of model creation, Eckhard noted that when creating IBIS
models from encrypted HSPICE models, model vendor must include enough
pre-driver stages so that the risetime of the input stimulus does not
effect the risetime of the final output stage. Five pre-driver stages
seems to be adequate. Eckhard also mentioned cases where models have
unreasonable lead-in time on V-T tables. The quality group should address
these issue in their checklist.
Eckhard also pointed out that different models have different min-typ-max
values for temperature and voltages, thus making it difficult to do
simulations in which devices are at mixed process/voltage/temperature
corners. He asked if all models should be supplied using the standard
default values called out in the IBIS specification. However, several
people noted that a processor, for example, will run hotter than a
memory device at a specific ambient temperature, so matching the min or
max temperature or voltage may not be critical, as long as the simulator
tool can pick a min or max model.
Finally, Eckhard observed that for modeling devices that run in the Ghz
range, the V-T and I-V table methodology gives accurate results, but the
current lumped package model is inadequate, and distributed pin/package
models are required.
PAD CAPACITANCE EXTRACTTION SPICE SIMULATIONS
Hazem Hegazy, Mentor Graphics
Bob Ross, Mentor Graphics introduced a method of extracting C_comp from
Spice models done by Hazem Hegazy. C_comp is important when doing overlay
comparisons of time responses.
Bob showed traditional time-domain ramp-up/ramp-down method and noted that
the results were dependent on the ramp speed. The proposal here is to use
a frequency domain sweep with an added inductor to search for the resonant
frequency of the tank circuit. This creates a very sharp resonance from
which the C_comp value is extracted. A small resistor can be added so that
the extraction can be done at any voltage.
Bob showed a plot of C_comp as a function of voltage for low and high state
settings. An average value is taken within the loaded DC voltage range.
This provides a good value that produces excellent correlation with the
source Spice code.
This method appears to give more reliable C_comp values than the time-domain
method. It is easy to implement. This proposal does not attempt to make
C_comp a function of voltage.
BUFFER IMPEDANCE AND IBIS QUALITY
Luca Giacotto, Alstom Transport
This presentation was a follow-on to Luca's last presentation given at the
March 2002 European IBIS Summit in Paris, France. In brief, Luca showed
that C_comp was both voltage and frequency dependent, and one way to model
a buffers input or output impedance was to use a pole-zero-pole model.
A proposed topology was implemented using an in-house simulator and the
results presented. Luca showed how the modified model compared with the
"IBIS-classic" model in a couple of time domain simulations. One case was
with reflections returned while the buffer was switching, the other case
showed reflections returning when buffer was done switching. The modified
model compared very favorably with the transistor level model.
Luca also showed that this pole-zero-pole behavior was present in other
devices by examining several models taken from the web. Finally, Luca
proposed a possible change in IBIS that would add a pole/zero table under
the [Model] keyword. This table would be used to describe a buffers input
or output impedance. Luca proposed adding enough parameters to cover both
the high and low states of an output buffer.
In a related discussion, Luca also showed how too few points in a [Power
Clamp] or [GND Clamp] I-V table will cause inaccurate estimates of an input
buffers impedance at a particular bias levels. He noted that for accuracy a
transistor model must include capacitance due to metal and pad (i.e. not
silicon related). Finally, Luca pointed out that by doing a frequency sweep
of the output impedance one can detect if there are not enough I-V point to
accurately estimate a buffer's input impedance and C_comp.
THE EVALUATION EXAMPLES OF CONNECTOR MODELING
Atsuji Ito, Matsushita Electric Industrial Co. (National/Panasonic)
The purpose of this presentation was to explain the necessity of connector
model extraction. Atsuji noted that some of the key factors considered in
the design of consumer electronics products are speed, quality, cost and
environment. (Japan is undertaking an effort to reduce the amount of lead
solder used in their manufacturing process). All of this drives the need
for accurate connector models. Atsuji stated that they are moving away
from bus-switch to less expensive connectors. He also noted that not all
connector vendors provide models, and even if they do they need the model
needs to be verified. For verification, one approach is to design an
evaluation board then use a TDR to extract parameters and determine pin
assignments. Atsuji noted that connector models are sensitive to variations
in solder, stating that just 0.1pf added cap due to solder made a 145pS
difference in delay between simulated vs. measured results. He also noted
that extracted vs. measured model crosstalk varies. Atsuji commented that
while extracted connector model are usually cast in SPICE, a SPICE model is
not always easy to use. He would like an IBIS like solution that enables
fast simulation (especially for floor planning).
IBIS INTERCONNECT SPECIFICATION
Stephen Peters, Intel Corporation
Stephen opened his presentation by stating that the Interconnect
Specification is undergoing a final editorial review and Revision 1.0 is
expected to be released for general review after the connector meeting on
June 20, 2002. Major changes since the last summit meeting include addition
of a "G" (loss) matrix, a nodal path description, S-parameter matrices, and
general clean-up and removal of redundant information. Stephen noted that
with the addition of the nodal path description format, the connector
specification encompasses both connectors and general purpose interconnect,
including package models.
In a quick overview of the technical details, Stephen stated that the
specification supports a single interconnect family; a family consists of
one or more individual models. Models are described in terms of such basic
information as maximum slew rate allowed, the model type (single line or
multi-line model), a path description, and information that allows the EDA
tool to map model pins to the rows of an LRGC or S-parameter matrix.
Stephen also noted that the specification supports three different types
of interconnect -- regular (no pins missing) and rectangular, regular and
non-rectangular, and irregular. Only regular interconnect is swathable.
Multi-line models (MLM) contain full coupling between pins or traces and are
intended to be used for simulations involving crosstalk and ground return
paths. On the other hand, single line models (SLM) do not support crosstalk
information and are primarily intended to model a pin under specific
conditions. Several different types of SLMs are available, including ones
created under even-mode, odd-mode and quiescent switching conditions.
Stephen noted that, for these models, the ground return path used to derive
the models values are documented in the models pin map.
Finally, Stephen pointed out that the data in the RLGC matrices can be
interpreted as either lumped elements or as per-unit-length values. This
interpretation is determined by a "Len" or "Mult" argument in the
path description and the [Derivation Method] keyword in the matrix section.
Lumped elements result from 3-D field solver extraction of irregular
structures, and are suited for describing most connectors. "Lump size" is
determined by the model created, and is based upon the maximum risetime the
connector is expected to support. On the other hand, per-unit-length values
result from 2-D field extraction and are suited for describing the parallel
traces in a package. Per-unit-length values are expected to be used in a
distributed transmission line model.
MULTI-LINGUAL MODELING APPLICATIONS AND ISSUES
Bob Ross, Mentor Graphics
Bob Ross stated that he was giving a brief summary of the BIRD75.1 proposal
based on previous presentations. He will then show just a few examples and
present a few issues.
Bob listed a number of benefits of multi-lingual support within
IBIS that are currently not adequately covered by the existing IBIS format.
These include advances in modeling details such as differential buffers,
controlled buffers, SCSI drivers, etc., and also more a complex die
interconnect description. A bonus is that IBIS can interface better with
true digital analysis through some existing analog/mixed signal (AMS)
languages. Bob then illustrated a number of these features using a sample
of a complex die that captures a number of real modeling requests and needs.
Bob stated that the multi-lingual approach leverages off of existing
investments in IBIS, Spice, VHDL-AMS, Verilog-AMS, etc. It still uses IBIS
for pinout, package, information and specification data, but calls and
executes external files when needed. Several EDA vendors including some
larger ones already offer multi-lingual products that use the above
languages and others. Other tools used in PCB design and analysis provide
another form of multi-lingual support by importing/exporting Spice code, so
such support is natural. The proposal will still recommend the existing
IBIS format as appropriate. The proposed extensions are limited to a few
new keywords and can provide a fast response to the existing industrial
needs. The new keywords are classified as:
[External Model] for models defined in other languages
[External Circuit] for die interconnect circuit extensions
[Node Declarations] and [External Call] for connecting everything together
Bob showed a reference model for an I/O buffer. The IBIS electrical
connections including power supply rails were shown. These were designated
as
D_drive, D_enable, and D_receive. Power supply voltages can be supplied by
explicitly defined interconnect or as implicit voltage within the external
model.
The syntax for [External Model] and [External Circuit] was described in
general terms. Each external reference contains four elements: name,
language, where the file is and the name of the model in the file, and the
interface ports. For Spice subcircuits and other language formats requiring
analog interfaces for digital controls, some additional A_to_D and D_to_A
subparameters are provided to translate digital control signals to or from
analog voltage levels. These voltages (such as 0 to 3.3 V or 0 to 1.0 V)
would provide the drive signals for Spice subcircuits. Threshold voltage
levels would be transformed to digital states. Some of the analog and
digital signal names would be reserved to promote model interchangeability.
In general, any name is acceptable.
The [External Model] keyword would reside within the [Model] keyword
(retaining Model_name as the name) and would override all other keywords and
subparameters under the [Model] keyword that describe electrical operation.
The [Model Spec] keyword is the only one that is not overridden.
The connection of the model is completed using the [Node Declarations] and
[Circuit Call] keywords. The die side of the pins are considered nodes with
the names as the pin numbers. Additional internal nodes are declared as
needed. The connection is by mapping ports to nodes in a manner that is
conceptually similar to using calls to Spice subcircuits. However, this can
be extended to include digital circuit interconnections.
Bob listed a few more aspects of the proposal. It covers differential
buffers (both true and based on single-ended buffers), series elements and
deals with all combinations of existing IBIS models and [External Model]s
connected directly to the die nodes or through [External Circuit] to the
die nodes. The Cell_port designation within [Circuit Call] keeps track of
what model is connected to what die node.
To illustrated extended capability, Bob showed two applications. One showed
that additional on die power distribution parasitic could cause waveform and
timing changes under SSO conditions. Another showed how a group in Europe
developing the Integrated Circuit Electromagnetic Model (ICEM) document is
attempting to add a core noise generator model to an existing IBIS models.
This core noise generator model adds power to ground currents due to on die
clocks networks.
Bob concluded that BIRD75.1 was still being discussed. Some points raised
on the IBIS reflector were listed. Based on some initial examination of the
proposal and trying to prototype some implementation, Bob noted that there
are some EDA vendor issues. One general issue is to confine the analysis
to just the nets of interest. It is possible to add too much interactive
connectivity. Another is to decide how an additional source is controlled.
This source could be controlled by stimuli on connected nets, by being set
up as an independent generator or by being controlled as if it were a model.
The application might dictate the best approach.
Bob concluded that BIRD75.1 will be processed and put forth for voting as
soon as possible.
IBIS VERSION 4.0 DISCUSSION
Stephen Peters, Intel Corporation
Stephen Peters began by summarizing the BIRDs proposed for IBIS 4.0 and
their relationship to BIRD75. This list was based on an e-mail exchange
between Stephen and Arpad Muranyi. The purpose of this summary was to
identify any BIRDS that may be candidates for removal because they are
difficult to implement and could be better accomplished by BIRD75
(multi-lingual models). However, the summary revealed that only two of
the 10 BIRDs have an effect on the simulation model: BIRD65.2 (C_Comp
refinements) and BIRD73.4 (Fallback Submodel). The rest are either
measurement specification additions, text only clarifications, or added
functionality unrelated to actual simulation.
Regarding BIRD65.2, it was noted that while this BIRD is easy to
implement, it could also be implemented via a multi-lingual model.
Furthermore, the whole idea of distributing C_Comp to improve model
accuracy may be superseded by the on-going work on frequency and
voltage dependent C_comp (refer to the BUFFER IMPEDANCE AND IBIS
QUALITY presentation earlier in the program). However, Stephen
pointed out that distributed C_Comp has already been implemented
in the HSPICE "B-element", and if it is removed then model creators
who develop models based on the B-element will not be able to transfer
this information using the IBIS data template. As there was no
compelling reason to remove this functionality, the consensus was
to leave the text for BIRD65.2 in the draft IBIS 4.0 specification.
Regarding BIRD73.2, arguments similar to that for retaining BIRD65
were presented. While the submodel functionality can be implemented
directly using a multi-lingual model, the fallback functionality is
relatively straightforward to implement in existing simulators.
Furthermore, the fallback function has been needed for several years.
Again, because no compelling reason could be offered to remove it, the
consensus was to leave the text for BIRD73.2 in the draft IBIS 4.0
specification.
Stephen stated that the final corrected draft of IBIS 4.0 will be given
a last reading at the June 28, 2002 teleconference meeting, with a
final vote scheduled for the first teleconference meeting in July.
IBIS OPEN PARSER DISCUSSION
Stephen Peters opened the discussion based on current IBIS reflector e-mail.
Stephen stated that he agrees that there are advantages in licensing the
IBIS golden parser under an open source arrangement, especially if the IBIS
Open Forum also offers the parser source code under the existing license
arrangement. However, Stephen asked why the emphasis has been on the
golden parser an not on the existing s2ibis (spice to ibis) program.
Stephen stated that if one wants to improve model quality, then improving
s2ibis is a better way to proceed. Improving the golden parser may insure
that more models are detected bad, but it will not improve the process of
making models. Stephen emphasized the difference between 'testing in
quality' and making it right in the first place, then suggested that the
IBIS quality committee look seriously at ways to improve s2ibis.
On the subject of funding and licensing, it was noted that many non EDA
companies have helped fund the development of the IBIS 2.1 and IBIS 3.2
parsers. It was felt that companies were willing to fund the development
because it advanced the industry and the IBIS standard. The point was
raised that perhaps non EDA companies would be less willing to fund future
development if the source code was now going to be available under open
source. During the discussion that followed it was suggested that an
informal poll be taken of the member companies to see how many would be
willing to fund the upcoming IBIS 4.0 parser development, even if the
source code was subsequently to be made available for free. It was also
suggested to find out how much each company would be willing to pay.
Stephen agreed to place these questions on the reflector and gather results.
OTHER DISCUSSIONS AND AD HOC PRESENTATIONS
Stephen Peters reported that the planned joint meeting between EIA and
JEDEC groups, scheduled for September in Vancouver, British Columbia was
canceled. The JEDEC group will still be meeting, but it is unknown if any
EIA affiliated group will be joining them. Given this turn of events, and
the fact that we already have a summit meeting scheduled for October at the
PCB East conference in Massachusetts, Stephen felt that scheduling a summit
meeting would not draw enough IBIS folks to make it worthwhile. Others
concurred. However, Stephen encouraged individual members to attend JEDEC
meetings of their choice. After discussion, Lynne Green volunteered to
attend the JC-16 JEDEC group meeting as an official IBIS representative and
report back to the IBIS group.
CONCLUDING ITEMS
Stephen Peters thanked the presenters for the great and informative
presentations. After noting the next teleconference meeting, Stephen
closed the IBIS Summit Meeting.
NEXT MEETING:
The next teleconference meeting will be on Friday, June 28, 2002 from
8:00 AM to 10:00 AM Pacific time.
============================================================================
NOTES
IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
stephen.peters@intel.com
Senior Hardware Engineer, Intel Corporation
M/S JF4-215
2111 NE 25th Ave.
Hillsboro, OR 97124-5961
VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 451-1871
lgreen@cadence.com
Senior Modeling Engineer, Cadence Design Systems
20 120th Ave NE, Suite 103, Bellevue, WA 98005-3016
SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
gdeburgh@innoveda.com
Senior Manager, Innoveda
1369 Del Norte Rd.
Camarillo, CA 93010-8437
LIBRARIAN: Roy Leventhal (847) 590-9398
roy.leventhal@ieee.org
Consultant, Leventhal Design and Communications
1924 North Burke Drive
Arlington Heights, Illinois 60004
WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
shuq@cisco.com
Manager, Hardware Engineering, Cisco Systems
170 West Tasman Drive
San Jose, CA 95134-1706
POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
jangulo@innoveda.com
Development Engineer, Innoveda
14715 N.E. 95th Street, Suite 200
Redmond, WA 98052
This meeting was conducted in accordance with the EIA Legal Guides and EIA
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ibis@eda.org
To send a message to the general IBIS Open Forum Reflector. This
is used mostly for IBIS Standardization business and future IBIS
technical enhancements. Job posting information is not permitted.
ibis-users@eda.org
To send a message to the IBIS Users' Group Reflector. This is
used mostly for IBIS clarification, current modeling issues, and
general user concerns. Job posting information is not permitted.
ibischk-bug@eda.org
To report ibischk2/3 parser bugs. The Bug Report Form Resides on
eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
bugs.
To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
/pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
/pub/ibis/bugs/s2iplt/bugsplt.txt respectively.
Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:
http://www.eigroup.org/ibis/ibis.htm
Check the pub/ibis directory on eda.org for more information on previous
discussions and results. You can get on via FTP anonymous.
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This archive was generated by hypermail 2b28 : Tue Jun 18 2002 - 14:56:34 PDT