Subject: RE: [IBIS] IBIS SUmmit minutes 6/13/02
From: Hassan Ali (Hassan.Ali@fidus.ca)
Date: Thu Jun 20 2002 - 13:27:04 PDT
I have a few questions relating to Eckhard's observations quoted below:
1. When models have "unreasonable" lead-in time on V-T curves I guess
the solution is to uniformly (i.e. for all the corners) trim the V-T
data so as to only remain with the rise or fall data that sufficiently
captures the rise/fall time. If by doing that, however, the time range
of the resultant V-T curves [i.e. for rise: time(Vhigh_max -
time(Vlow_min) ]is greater than the bit-width, what would be the best
way to correct the model?
2. If for a given SPICE model, the output slew-rate of the buffer is
dependent on the slew-rate of the input stimulus, what would be the best
way to create useful V-T curves? Is their a rule-of-thumb for the
suitable slew-rate of the input stimulus?
3. Could anyone explain using a simple (driver->transmission line->load)
example how different simulators use V-I and V-T curves of an IBIS model
to compute voltages/currents on circuit nodes?
Thanks.
Hassan.
-----Original Message-----
From: Guy deBurgh [mailto:gdeburgh@innoveda.com]
Sent: Tuesday, June 18, 2002 5:30 PM
To: ibis@eda.org
Subject: [IBIS] IBIS SUmmit minutes 6/13/02
...
On the subject of model creation, Eckhard noted that when creating IBIS
models from encrypted HSPICE models, model vendor must include enough
pre-driver stages so that the risetime of the input stimulus does not
effect the risetime of the final output stage. Five pre-driver stages
seems to be adequate. Eckhard also mentioned cases where models have
unreasonable lead-in time on V-T tables. The quality group should
address
these issue in their checklist.
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