RE: [IBIS-Users] parasitic ESD simulation

Hi, Ramiro,

Physically, the p-n (drain-body) junction of the PMOS turns on. Also, if
the output pin goes above Vcc+Vth_fet, the PMOS can turn on, with current
flowing from the output to the power supply. ("source" becomes "drain"
under these bias conditions.)

Older SPICE models did not accurately represent the diode clamping of the
FET junctions; I am not sure if that is still true in BSIM4.

Also, some fabs might not characterize the relevant parameters accurately,
since this requires driving the device outside its "normal" operating
region. I have heard reports of as much as a factor of 10 difference
between SPICE and measurement. A check against measurements is a good way
to catch SPICE parameter problems.

- Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of RODRIGUEZ_LECONA_RAMIRO
Sent: Thursday, October 28, 2004 9:51 AM
To: ibis-info@eda.org; ibis-users@eda.org
Subject: [IBIS-Users] parasitic ESD simulation

Hi all again:

       I have a question about Power Clamp and Ground Clamp curves. Some IC
designers use the buffer's output transistors like ESD protection devices.
They use the transistor's PARASITIC DEVICES to protect the circuit, i.e. the

clamps are not explicit. Since this protection is based essentially on
layout techniques (areas, corners, etc) and the transistor model (BSIM) does

not model the parasitic devices (maybe I am wrong about it ??) How can I
simulate correctly the clamp behavior ?. I have simulated from a simple
netlist this situation and I get curves that behave like diodes!!! But this
curves what represents? It is the true behavior of clamps?
        How do you face this situation?

Best Regards,

Ramiro. R. Lecona
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Received on Thu Oct 28 10:17:48 2004