Hello, How do we ensure that IBIS model can be correctly simulated at the highest possible frequency? Suppose, I have a buffer which is expected to work at 100MHz. Hence, the VT table should be at most 1 / ( 2 * 100M ) = 5ns wide. If the buffer is designed such that it can just meet this requirement in min (slow) corner. The problem that I am facing is that I cannot represent all of typ/min/max transitions within this window of 5ns because of variations in buffer delay across corners. How do I create an IBIS model that can be correctly simulated at 100MHz in such cases? Thanks for your help. Gowtham -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean. -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993Received on Mon May 18 07:58:21 2009
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