Re: [IBIS-Users] question about IBIS simulation for a complete inverter

Hello, Ji,

It is not clear exactly what you wish to accomplish with your simulation.

Some things to consider about IBIS buffer models:
* Input buffer has ONE pin (its input). No output pin. So the input
can never
"drive" an output buffer. That is why (as Tom pointed out) there is no
delay
information for input buffers.
* Output buffer has ONE pin (its output pin). While it is possible to
use DATA as an analog input, a deeper knowledge of the simulator would
be helpful. For example, some SI simulators use a threshold crossing
to begin the output toggle, so there is no "transfer function".
* Load determines the time it will actually take to complete the toggle
at the output pin.
Interconnects (traces) on boards are transmission lines and are
resistive rather than capacitive.
Interconnects on chips are also transmission lines, but tend to be
capacitive.

If, on the other hand, you are comparing an IBIS buffer with the netlist
it was
created from, that is much easier. One applies the same load to the two
units
and compares the simulation results. For the load used to create the model,
the two simulation results should match.

Hope this helps.

Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com

*From:* owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] *On
Behalf Of *ji xiao
>
> *Sent:* Wednesday, March 17, 2010 11:35 PM
> *To:* tom@teraspeed.com
> *Cc:* ibis-users@eda.org
> *Subject:* Re: [IBIS-Users] question about IBIS simulation for a
> complete inverter
>
>
>
> Dear Tom,
>
> I agree with your statement that there is no description of the logic
> function in IBIS model. Then, if I just want to compare the IBIS
> simulation result of a complete inverter with its PSPICE simulation
> result, do I need to simulate the output model only or cascade the
> IBIS input model with the output model? It seems that the cascading
> way will be closer to the PSPICE result, but I am not sure. I just
> directly treat the output signal of the input model as the input
> signal of the output model.
>
> Thanks and regards,
>
>
>
> Ji Yuancheng
>
> On Thu, Mar 18, 2010 at 12:17 AM, Tom Dagostino <tom@teraspeed.com
> <mailto:tom@teraspeed.com>> wrote:
>
> Ji
>
>
>

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