[IBIS-Users] RE: [IBIS-Users] ´ð¸´: [IBIS-Users] A question about the ibis simulation.

Naftali,

I hope you don't mind a few practical suggestions from another IBIS modeler. This is a great question for the SI List.

In my opinion, the spike has nothing to do with the IBIS model itself and I will explain how to prove it. In this case I would suggest that the output driver impedance mismatches the T-line impedance, therefore we are seeing a reflection due to this EM boundary condition. A real world example would be a pair of eye-glasses, without anti-reflective coating to match the light propagation impedance of glass to air: other people see some reflection of themselves in your glasses.

First of all, common CMOS output drive impedance values are 18 ohms, 22 ohms, and 34 ohms (contact your IP vendor). Secondly, the RLC discontinuity of a package will fold into the rise and fall of the waveform, because it is located too close to the driver for too short a distance to affect the signal (otherwise it is the incorrect package). Therefore, remark these out of the IBIS file, and you'll see the same reflection in your simulation cases.

For the next set of sims, I would suggest a series termination resistor on your T-line rather than the end-termination scheme shown here. The series termination must be placed within the Tr propagation of the signal (for example, within 1" of a driver having a 400ps risetime). The IP vendor should be able to provide the source driver impedance value. Alternatively, if you remark out the package RLC values in the IBIS file, and perform bracketed simulation of various series-impedance values, this will reveal the output driver's characteristic impedance by process of elimination. Finally, a 1000 Ohm resistor is very strange value for CMOS driver impedance. It is 10x too large for most parallel terminator- and this parallel termination scheme is basically incorrect.
- Series termination: Assign a 33 ohm resistor for 18 ohm driver within the T-rise propagation distance of the output driver.
- Parallel termination: Terminate 25 ohms to a VDD/2 to a supply capable of sinking and sourcing current, such as a DRAM VTT regulator with adjustable VTT value. Or, terminate to the center tap of VDD -> 25 Ohms -> tap -> 25 Ohms -> VSS.

It would be helpful if you mentioned what kind of interface you intended to model. This is not clear. But you are showing steep rise times for the throughput rate, almost 100x. The channel capacity you're asking for is 0.5/Tr (Credit: Dr. Johnson. For example, 0.5/400ps = 1.25GHz channel BW). So, to minimize concerns about channel capacity and EMI, it would be best to reduce the output drive strength or install 1000pF capacitor shunts to VSS near the transmitter. A basic target is to reduce (or adjust) the rise time to just over 2x of the clock signal frequency.

On a practical note, there is no such thing as a 50.0-ohm trace on a PCB. Modern consumer product PCB limitations result in a value of more like 55 or 60 ohms, and are always +/- 10%. Finally, make sure your trace follows a path where return-current can follow a channel good from DC to 1.25GHz BW, if this is your intent.

Best regards,

Graham Kus
Sr. HW Dev Engineer
Certified SI Engineer

________________________________________
From: owner-ibis-users@eda.org [owner-ibis-users@eda.org] On Behalf Of Lynne D. Green [lgreen22@mindspring.com]
Sent: Wednesday, July 06, 2011 5:22 PM
To: Zhanggezi
Cc: 'ibis-users'; 'yang@huawei.com'
Subject: Re: [IBIS-Users] ´ð¸´: [IBIS-Users] A question about the ibis simulation.

You need to look at the assigned parasitics for each component. One way to see these are to export the SPICE model and look at the netlist. Another way is to select each component and look at its properties.

What you are looking for:
What parasitics are assigned for the resistor?
What parasitics are assigned for the driver package?
What parasitics are assigned for the receiver package?

These parasitic values might come from the IBIS file at the Component, Pin, or Package level. Parasitic values might also be set to a default for "standard package" parts.

- Lynne



On 7/6/2011 3:35 AM, Zhanggezi wrote:
Hi All,

The topology is below. And ibis file is very large, I will share with you if needed after deleting unnecessary information.
[cid:part1.08030607.05080508@mindspring.com]

And the probe is on the receiver, three simulation outputs are different corners for one model(fast,typical and slow corners), and I
Want to the reason for the spike. Any one can help?
[cid:part2.00020404.09060501@mindspring.com]

·¢¼þÈË: owner-ibis-users@eda.org<mailto:owner-ibis-users@eda.org> [mailto:owner-ibis-users@eda.org] ´ú±í Muranyi, Arpad
·¢ ËÍʱ¼ä: 2011Äê7ÔÂ5ÈÕ 23:52
ÊÕ¼þÈË: 'ibis-users'
Ö÷Ìâ: RE: [IBIS-Users] A question about the ibis simulation.

Naftali,

I am not sure I understand what the ¡°The topology is one on one¡± is
referring to in the original question. So I am not sure what
you mean by ¡°set a very same length to both T branches¡± either. Please
clarify your question.

Thanks,

Arpad
==============================================================

From: naftali refaeli [mailto:Naftali.Refaeli@ecitele.com]
Sent: Tuesday, July 05, 2011 10:49 AM
To: Muranyi, Arpad; 'ibis-users'
Subject: RE: [IBIS-Users] A question about the ibis simulation.

Do you mean that If he will set a very same length to both T branches ¨C then the phenomenon will disappear?


Naftali Refaeli
CAE Engineer
ITO
HP Enterprise Services
Telephone +972 3.9266973
Mobile +972 52.3542043
Email Naftali.Refaeli@ecitele.com<mailto:Naftali.Refaeli@ecitele.com>

From: owner-ibis-users@eda.org<mailto:owner-ibis-users@eda.org> [mailto:owner-ibis-users@eda.org] On Behalf Of Muranyi, Arpad
Sent: Tuesday, July 05, 2011 6:45 PM
To: 'ibis-users'
Subject: RE: [IBIS-Users] A question about the ibis simulation.

Grace,

It looks like that the first ledge is the voltage that the
driver can drive with the load imposed on it by the T-line.
Once the reflection comes back to the driver the voltage
steps up to the full swing levels. This is basic T-line
theory.

Arpad
============================================================

From: owner-ibis-users@eda.org<mailto:owner-ibis-users@eda.org> [mailto:owner-ibis-users@eda.org] On Behalf Of Zhanggezi
Sent: Monday, July 04, 2011 8:54 PM
To: 'ibis-users'
Subject: [IBIS-Users] A question about the ibis simulation.




Hi All,



  The topology is one on one. The simulation result is below. I am curious about the simulation circled



by red pink. What¡¯s the cause? Could someone give me any hint?



  [cid:part3.01000909.07010805@mindspring.com]



Thank you.



Grace

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Received on Wed Jul 6 21:38:05 2011