Re: Characterization Conditions

Rob,

In the case of a classic GTL driver (which uses feedback), you may also
want to sweep the resistance to Vtt (Rterm) over its effective operational
range. Then compare behavioral simulation waveforms against SPICE
waveforms and see how close you can get. I found that the simulator I was
using wasn't able to track SPICE very well. I've been told that multiple
VT tables for different values for Rterm is one approach to solving the
"GTL feedback behavioral modeling problem," but I've never actually heard
the circuit theory behind this.

I guess all I'm saying is run some SPICE vs. behavioral correlation and
"model developer beware..."

Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

Rob Eccles <rob.eccles@xilinx.com> on 12/17/98 07:57:28 PM

To: Stephen Peters <sjpeters@ichips.intel.com>
cc: ibis@eda.org, ibis-users@eda.org (bcc: Gregory R
      Edlund/Rochester/IBM)
Subject: Re: Characterization Conditions

Hi Steve,

Thanks for your prompt reply!

After reading your response, and giving it some more thought,
it looks like SSTL and HSTL should use the same methodology
given in Table 1 for CMOS (from the 2.0X version of the Cookbook).

In practise, not all boards will use 50 Ohm loads. How sensitive
are the IBIS models to termination resistance? I would expect
this to be significant.

Regards,
Rob Eccles
Xilinx

Stephen Peters wrote:
>
> Hello Rob:
>
> By "recommended characterization conditions" I assume you mean
> the output loads/voltages use to extract V/T waveforms. Because the
> GTL/GTL+ outputs are open-drain, I would extract the V/T waveforms
> using the rules for open drain buffers -- a load resistor to
> Vterm, with the value of Rterm and Vterm determined by the
> specification or part manufacturer. As for the other standards,
> if the driver uses a standard push/pull structure use the rules for
> standard CMOS or TTL (depending on the technology of the buffer).
> Remember: by taking the V/T waveforms with a load tied
> to Vcc then to ground, one can isolate the turn-on, turn-off and
> overlap times of the pullup and pulldown structures, thereby allowing
> the simulator to construct an accurate model of the driver. This
> model should be accurate, even if the driver application calls for
> the output to be terminated to Vcc/2, or series terminated, or whatever.
>
> Regards,
> Stephen Peters
> Intel Corp.
>
> > I have read with interest the latest version of the
> > IBIS cookbook. It details recommended characterization
> > conditions for simulating TTL, ECL, LVCMOS, etc. It
> > does not contain recommended conditions for measuring
> > newer I/Os, i.e. SSTL, HSTL, GTL, LVDS.
> >
> > What are the recommended simulation conditions for these
> > I/Os?
> >
> > Rob Eccles
> > Xilinx
> > rob.eccles@xilinx.com
Received on Fri Dec 18 05:51:30 1998