Re: Characterization Conditions

Rob,

Many simulators are interested in using results of driving the TRACE
IMPEDANCE seen by the driver which is where the 50 came from. Vaguely
speaking--using the range of the DC V-I curves exercised by the VT loading
conditions together with the AC waveform data as inputs, the driver may then
be applied to arbitrary loads (termination, capacitance, diodes, ...) in
simulation to produce accurate results.

So as long as the load is near (e.g. within .25X to 4X) the impedance that
the driver sees during switching, simulation results should be nearly
identical for most devices.

DISCLAIMER: Simulators are not required to use the waveform data in any
particular manner so the above may not be true for all simulators. However
the cookbook recommendations were developed under consensus of simulator
companies on the IBIS committee.

Regards,

Chris Rokusek
Viewlogic Systems

-----Original Message-----
From: Rob Eccles <rob.eccles@xilinx.com>
To: Stephen Peters <sjpeters@ichips.intel.com>
Cc: ibis@eda.org <ibis@eda.org>; ibis-users@eda.org <ibis-users@eda.org>
Date: Thursday, December 17, 1998 6:43 PM
Subject: Re: Characterization Conditions

>Hi Steve,
>
>Thanks for your prompt reply!
>
>After reading your response, and giving it some more thought,
>it looks like SSTL and HSTL should use the same methodology
>given in Table 1 for CMOS (from the 2.0X version of the Cookbook).
>
>In practise, not all boards will use 50 Ohm loads. How sensitive
>are the IBIS models to termination resistance? I would expect
>this to be significant.
>
>Regards,
>Rob Eccles
>Xilinx
Received on Fri Dec 18 09:50:34 1998