Primer on ECL logic

Hello Fellow Ibisians --

        As promised during the open forum:

  VCC (0v) ---------------------------------------------------------
                | | |
                | | |
                R1 R2 |
                R1 R2 |
                R1 R2 |
                | | /
                | | |
                | |---------------------| Q3
                | | |
                | | \
               / \ |
              | | |
  INPUT ------| Q1 Q2 |--- VREF (-1.4) |
              | | ---------------- OUTPUT
               \ / |
                | | |
                | | |
                | | RT
                ----------------- RT
                        | RT
                        | |
                        | |
                      ----- |
                 Constant current ----
                      sink VTT (-2v)
                      -----
                        |
                        |
                        |
                       VEE (-4.5v)

     The above is a highly simplified schematic of an ECL logic gate. ECL
logic levels swing between -.9v to about -1.8v, centered around the VREF
voltage reference inside the chip. Assume for a moment that the INPUT is
at -.9v. Because Vbe across Q1 is much greater than that across Q2, Q1
supplies the current required by the constant current sink and little
current flows thru the collector of Q2. Will little voltage
drop across R2, the base of Q3 is pulled towards the positive rail which
in turns pulls the OUTPUT node more positive. Now assume that the INPUT
node is at -1.8v. Q1 will be close to cutoff and the current required by the
constant current sink is supplied by Q2. The voltage drop across R2
increases, thus pulling the base of Q3 low and the OUTPUT node goes
along with it.
     As you can see, the difference between an output in a 'high'
(more positive) state and an output in a low (more negative) state is
simply the voltage at the base of the output emitter follower xsistor.
In fact, in regards to generating VI curves, what you are really graphing
is the Ie Vs. Vbe characteristics of the output xsistor; in one case Vb is
at -.3v, in the other it is at -1.2v. In either case, the output
voltage is always referenced to the VCC rail.

     I hope this diagram and explanation helps. For those that are really
interested I suggest the "MECL Design Handbook" by William Blood from Motorola.

        Best Regards,
        Stephen Peters
        Intel Corp.
Received on Fri Sep 10 15:08:27 1993