Re: Primer on ECL logic

Hi Stephen,

This is another two cents worth of advice about the difference of
CMOS and ECL as I can see:

For the CMOS output buffer, without looking inside the circuit, one
technique to find the voltage reference is: sweep the output node
voltage until the current is 0. The neccessary conditions for this
to happen is only one of the device is on, and it is operating in the
common-source mode (which means the gate and source voltage determines
the on/off of the transistor). In ECL, the output stage in common-emmitter
mode and both pull-up and pull-down device are on. Therefore output
current will zero somewhere between 0 and VTT, the voltage is around
    Iq2 * R2 + 0.6, assume Vcc==0.
The reference voltage for each state will be a function of Iq2 instead
of a voltage. Of course, Iq2 is the function of the input voltage
at Q1.

Siuki Chan
Logic Modeling

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Received on Mon Sep 13 09:30:39 1993