Subject: [IBIS] Time scale for VT plots on IBIS model.
From: Baumann, Hans-Gerhard (HGBaumann@ti.com)
Date: Wed Nov 13 2002 - 06:51:56 PST
I am working to generate IBIS models for "zero delay buffers". The main
building block is a internal PLL. One differentiation between different
products is the phase relation between input and output. Different products
have different phase.
I thought, in system simulation it might be interesting if the IBIS model
reflects the "locked phase" on its VT-tables. This however might require
that a negative start time is acceptable. I am not sure if this is OK with
current IBIS spec (working with version 3.2) or if there are plans to accept
this in future.
Any recommendation on that ?
Best Regards,
Gerd Baumann
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