Subject: RE: [IBIS] Time scale for VT plots on IBIS model.
From: Muranyi, Arpad (arpad.muranyi@intel.com)
Date: Wed Nov 13 2002 - 12:40:15 PST
No there is no "real" negative delay, not even for a PLL.
What you see there is a consequence of a few cycles that
happened before...
Arpad Muranyi
Intel Corporation
==========================================================
-----Original Message-----
From: Ingraham, Andrew [mailto:Andrew.Ingraham@hp.com]
Sent: Wednesday, November 13, 2002 11:26 AM
To: ibis@eda.org
Subject: RE: [IBIS] Time scale for VT plots on IBIS model.
> This buffer delay might be negative in some cases in order to
> correlate with the other simulations. Don't worry too much about
> negative delays of parts of the circuit. This is a possible and
> logical byproduct of the way we measure the sections of the overall
> circuit in different simulators. When you add up the component
> propagation delays with interconnect delays, then the sum should be
> positive.
In this case, the negative delay is real. The part is a PLL, which
creates a replica of the input, using an internal oscillator. From the
outside terminals, when in-lock, it looks like a buffer that has zero
delay ... or slightly positive, or negative ... depending on the
feedback loop.
But the other question is, exactly what do you want to use the IBIS
model for? I use them to represent the input buffer, or the output
buffer, of an IC. But not both at the same time. I don't use them to
represent the whole path from input pin to output pin; and I don't think
IBIS models are suitable for doing that.
SPICE models could do that; but even most SPICE models from vendors
don't; they represent just the input OR output buffers.
Andy
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