Subject: RE: [IBIS] Time scale for VT plots on IBIS model.
From: Ingraham, Andrew (Andrew.Ingraham@hp.com)
Date: Wed Nov 13 2002 - 13:53:34 PST
> No there is no "real" negative delay, not even for a PLL.
> What you see there is a consequence of a few cycles that
> happened before...
That is true.
But as you vary the frequency, within limits, the effect is that the
*apparent* delay through the part is some small value (~independent of
frequency) which could be negative.
In reality there is no such thing as delay through a PLL. There is no
path from "input" to "output". They only seem to have one.
Andy
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