ASIAN IBIS SUMMIT (TOKYO) AGENDA

Friday, November 17, 2017

Organizational Sponsors:

Japan Electronics and Information

Technology Industries

Association (JEITA)

IBIS Open Forum

Sponsors: ANSYS, Inc.

Cadence Design Systems

Cybernet Systems

Keysight Technologies

Ricoh

Toshiba Coproration

Zuken, Inc.

Minutes: m111717.pdf

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13:30 SIGN IN

13:35 MEETING WELCOME

- Mike LABONTE (SiSoft, USA)
  Chair, IBIS Open Forum

- Mitsuharu UMEKAWA (Keysight Technologies, Japan)
  Chair, JEITA EDA Model Specialty Committee

13:45 IBIS Update

Mike LABONTE (SiSoft, USA)

14:10 What's Expected for IBIS-AMI from the Perspective of End-User Support

Masao NAKANE (Xilinx, Japan)

14:40 DDR System Simulation: What Issue to Simulate

Shinichi MAEDA (KEI Systems, Japan)

15:10 BREAK

15:30 Investigation of the Package Crosstalk Noise to DDR4-IF Signal by

IBIS [Define Package Model]

Akiko TSUKADA, Masaki KIRINAKA

(Fujitsu Interconnect Technologies Limited, Japan)

[Presented by Akiko TSUKADA

(Fujitsu Interconnect Technologies Limited, Japan)]

16:15 On die De-cap Modeling Proposal

Kazuki MURATA (Ricoh Company, Japan)

16:40 IBIS Interconnect Modeling Using IBIS-ISS and Touchstone

Michael MIRMAK (Intel Corporation, USA)

[Presented by Mike LABONTE, (SiSoft, USA)]

17:15 CONCLUDING ITEMS

17:30 END OF IBIS SUMMIT MEETING