RE: [IBIS-Users] Information on Vref, Rref & Cref

I was somewhat confused about the loading question and reply.
 
Rref and Cref are for timing checks, not for simulation.  The loading for
V-t tables is R_fixture.  So both are needed in a model.

One should not use reactive loading in a V-t table.  This has been observed
to "break" the algorithm as implemented by some SI tools.

The underlying algorithms have been published in two papers:
* The Development of Analog SPICE Behavioral Model Based on IBIS Model
Ying Wang & Han Ngee Tan  
 * Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS
P. Tehrani, Y. Chen & J. Fang

- Lynne 


"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com


________________________________

	From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Alex Hilbers
	Sent: Wednesday, January 10, 2007 1:47 AM
	To: Sudarshan Honnudike; ibis-users@eda.org
	Subject: RE: [IBIS-Users] Information on Vref, Rref & Cref
	
	
	Sudarshan,
	 
	Interesting question. I always wondered how a table based model
(V-I, ..), such as an IBIS model, could model any form of feedback control
system, as the IO pad you describe probably is. It seems that V-t waveforms,
together with a simulation tool specific algorithm, must do that job. You
verify this by comparing your simulation tool with actual SPICE results.
This is prone to variation based on which tool you use, I donot think this
'algorithm' is standardised. To my knowledge XTK needs the curves
rising/falling, for load to VCC and GND (i.e. all 4), otherwise the V-t
tables are ignored. (Some vendors do provide only 1 or 2, which is useless).
Interesting is what happens if you define several load conditions (Rfixture
= 25, 50, 75 Ohms), not to mention capacitive and inductive loading. What
will the simualtion tool choose, will it interpolate, I donot have the
faintest idea. I guess it won't work within IBIS, which may be the reason
you do not get answers. 
	 
	Maybe a good reason to provide SPICE models for this type of buffer.
Either under NDA or encrypted. Level 50 HSPICE, i.e. Philips MOS Model 9,
should be fine. 
	 
	Best regards,
	
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	Alex Hilbers 
	Signal Integrity Analysis and Thermal Management, ASML, EDEV
department

	Building 7J0005, P.O. Box 324, 5500 AH Veldhoven, The Netherlands
	Phone: +31-(0)40-268 5587, Fax: +31-(0)40-268 5530
	Email: alex.hilbers_ f rom _asml.com, www.asml.com <http://www.asml.com/> 
	

		 

________________________________

	From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Sudarshan Honnudike
	Sent: Wednesday, January 10, 2007 6:35 AM
	To: ibis-users@eda.org
	Subject: [IBIS-Users] Information on Vref, Rref & Cref
	
	

	Hi , 
	
	If we have a IO pad which works in the different applications
depending on the load applied 
	on it, then do we to  provide V-t waveforms(more than normal 4
curves) for different applications 
	with different load settings.? 
	
	Or can we specify that loading conditions under Rref, Vref and Cref
for that model. Which one is preferable. ? 
	
	I tested my model with Hyperlynx SI tool and it is not identifying
the Rref and Vref values that I am specifying 
	in my model. It will only take Cref and Vmeas while doing
simulations. In that case we can't specify the loading 
	conditions under Vref, Cref and Vref but we need to give all
possible V-t curve combinations for different loading conditions. 
	
	Please let me know your reply. 
	
	PS : I am also waiting for the reply to my previous mail regarding
Common Mode Voltage Range support in IBIS . 
	
	Best Regards,
	
	Sudarshan HN
	NXP Semiconductors/CTO /PLT
	C-4, Manyata Tech Park, Nagawara
	Bangalore-560 045 , India.    
	Ph:+91-80-40267073  
	Fax: +91-80-4026 7855
	seri:sudarsha@inpsblr
	E-mail: sudarshan.honnudike@nxp.com
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